BBD SPICE Model
I've built a SPICE model so I can play with clock, bias, and filter circuits for BBD projects. It seems to perform pretty close to a real one, though I have drawn only 8 stages to keep simulation times practical. The biasing and distortion behavior seem pretty close to Panasonic datasheets for 32xx series. Being 8 stages, the delay time is very small, but does visibly change with clock rate as expected. The capacitive load simulates a 3205 (4096 stages), but can be easily adjusted.
- Attachments
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- Partial Image of BBD Schematic
- BBD Model.png (9.89 KiB) Viewed 2667 times
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- NMOS BBD 5.zip
- BBD Spice Model (Tina-TI)
- (8.27 KiB) Downloaded 247 times
- Dirk_Hendrik
- Old Solderhand
Information
Just doing a little looking into recreating this in LTSpice, and I found a new models for the Transistors
http://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf
I'll see if I can get this working, and upload what I get
http://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf
I'll see if I can get this working, and upload what I get