http://www.edn.com/article/CA223208.html
So... what would be the max. delay time (theoretical, not necessarily using the part values shown) if you used a PWM frequency of 20kHz?
how to calculate a chip's delay time
- earthtonesaudio
- Transistor Tuner
rocklander wrote:hairsplitting and semantics aren't exactly the same thing though.. we may need two contests for that.
- earthtonesaudio
- Transistor Tuner
Okay I figured it out (I think... )
And based on this I think I have an idea for a hi-fi analog delay.
1. Audio gets converted to PWM
1a. A portion of the audio is sent to the output mixer before PWM conversion
2. PWM signal is split into rising- and falling-edge paths
3. Each path is delayed using a large FIFO (one for each side) organized as a shift register
3a. Delay through the FIFO is determined by the clock frequency (which should be at least 2x the PWM frequency)
4. Rising edge triggers Set, falling triggers Reset in an SR flip-flop, which thereby reconstructs the pulse width information
5. PWM output is filtered to remove high frequency harmonics-->into output mixer-->audio output
6. A portion of the audio output is fed back to the audio input (regen for flangers, repeats for delays)
With a large enough FIFO and a high enough sample rate, I believe you could make an analog (yes I'm pretty sure this would be considered analog) delay with NO degradation.
Bonus:
In theory, only one of the edges needs to actually pass through a delay. The other could be "faked" with an astable or by dividing the FIFO clock.
And based on this I think I have an idea for a hi-fi analog delay.
1. Audio gets converted to PWM
1a. A portion of the audio is sent to the output mixer before PWM conversion
2. PWM signal is split into rising- and falling-edge paths
3. Each path is delayed using a large FIFO (one for each side) organized as a shift register
3a. Delay through the FIFO is determined by the clock frequency (which should be at least 2x the PWM frequency)
4. Rising edge triggers Set, falling triggers Reset in an SR flip-flop, which thereby reconstructs the pulse width information
5. PWM output is filtered to remove high frequency harmonics-->into output mixer-->audio output
6. A portion of the audio output is fed back to the audio input (regen for flangers, repeats for delays)
With a large enough FIFO and a high enough sample rate, I believe you could make an analog (yes I'm pretty sure this would be considered analog) delay with NO degradation.
Bonus:
In theory, only one of the edges needs to actually pass through a delay. The other could be "faked" with an astable or by dividing the FIFO clock.
rocklander wrote:hairsplitting and semantics aren't exactly the same thing though.. we may need two contests for that.